1. Field of the Invention
The present invention relates to a mixer circuit for frequency mixing of electrical signals.
2. Description of the Related Art
Frequency mixer circuits multiply two input signals with different frequencies and presents at their output a mixture of signals with new frequencies. They are used as frequency converters mainly in radio communication equipment such as cellular phones. Specifically, frequency mixer circuits (hereafter “mixer circuits”) serve as upconversion mixers that convert an intermediate frequency (IF) signal to a radio frequency (RF) signal or downconversion mixers that convert an RF signal to an IF signal.
For portability, cellular phones are required to operate at a low supply voltage from batteries, with low power consumption, besides being small and lightweight. Accordingly, the mixer circuit used in such cellular phone devices is also required to operate properly at a low supply voltage.
As an example of conventional mixer circuits, a circuit structure using two stages of output transistors is proposed in Japanese Patent Application Publication No. 2003-234619, paragraph Nos. 0015 to 0017, FIG. 1 (referred to hereafter as “conventional technique #1”). Another example is a circuit structure using a single stage of output transistors, which is shown in Japanese Patent Application Publication No. 10-275193 (1998), paragraph Nos. 0022 and 0023, FIG. 2 (referred to hereafter as “conventional technique #2”).
One drawback of such conventional mixers used in radio communication equipment is their narrow linear range, which distorts their output signals under low supply voltage conditions. In this technical field, a measure known as “output 1-dB compression point” (O1CP) is used to represent linearity performance of a circuit. O1CP of an electronic circuit refers to the output amplitude at which its linearity is reduced by 1 dB. For smaller input signals within a certain voltage range, the circuit exhibits a good linearity; i.e., the output voltage is proportional to the input voltage. The circuit, however, begins to behave in a non-linear fashion as the input voltage level is increased further. In this non-linear range, the actual output voltage falls below the theoretical output voltage. In other words, the input/output curve of a circuit deviates from its ideal linear curve. The deviation exceeding 1 dB means noticeable distortion of the output signal, or significant performance degradation.
As described above, O1CP of an electronic circuit indicates how linear it is; a higher O1CP value means a wider linear range. O1CP is degraded as the supply voltage decreases. It is therefore a challenge for the design engineer to minimize the degradation of O1CP so that the circuit can operate with sufficient linearity even under low supply voltage conditions.
Referring now to FIGS. 30 to 32, more details of conventional techniques #1 and #2 will be described below, including their shortcomings.
FIG. 30 illustrates a mixer circuit structure according to conventional technique #1. The illustrated mixer circuit 100 is formed from four P-channel metal oxide semiconductor (MOS) transistors MP1 to MP4, six N-channel MOS transistors MN1 to MN6, and two resistors RL1 and RL2. These components are arranged as follows.
One RF input terminal (RFin) is connected to the gate of transistor MP1. Another RF input terminal (RFinX) is connected to the gate of transistor MP2. One LO input terminal (LOin) is connected to the gates of transistors MN1 and MN4. Another LO input terminal (LOinX) is connected to the gates of transistors MN2 and MN3.
Power supply voltage Vdd is connected to the sources of transistors MP4 and MP3, as well as to one end of resistors RL1 and RL2. The gate of transistor MP4 is connected to the drain of transistor MP4 itself, the gate of transistor MP3, and the drain of transistor MN7.
The drain of transistor MP3 is connected to the sources of transistors MP1 and MP2. The drain of transistor MP1 is connected to the drain of transistor MN5, as well as to the sources of transistors MN1 and MN2. Likewise, the drain of transistor MP2 is connected to the drain of transistor MN6, as well as to the sources of transistors MN3 and MN4.
One IF output terminal (IFout) is connected to the other end of resistor RL1, as well as to the drains of transistors MN1 and MN3. Another IF output terminal (IFoutX) is connected to the other end of resistor RL2, as well as to the drains of transistors MN2 and MN4. Bias terminal is connected to the gates of transistors MN5, MN6, and MN7. The sources of transistors MN5 to MN7 are connected to the ground.
In operation, a differential pair of radio frequency signals RF (i.e., complementary signals RFin and RFinX) are converted into a differential pair of current signals by transistors MP1 and MP2. The resulting signals are directed back to differential transistor pairs MN1-MN2 and MN3-MN4 by transistors MN5 and MN6 serving as current sources. Differential local signal LO (i.e., complementary signals LOin and LOinX) switches their current paths, thereby multiplying the radio frequency signal RF by the local signal LO. The multiplication result is obtained as a differential pair of IF signals at one end of each load resistor RL1 and RL2.
The above-described conventional technique #1 is an application of Gilbert cell, which is an electronic multiplying mixer widely used in various fields. The Gilbert cell mixer is characterized by its cascode output section using two stacked transistors. One drawback of this cascode configuration is its limited linear range. This is also true for the conventional mixer circuit 100.
Specifically, the output section of the illustrated mixer circuit 100 is configured as a cascode of a differential MOS transistor pair MN1-MN2 and a single MOS transistor MN5, together with a cascode of another differential MOS transistor pair MN3-MN4 and another single MOS transistor MN6.
As mentioned earlier, those transistors MN1 to MN6 are N-channel MOS transistors. To make such N-channel MOS transistors operate in their saturation range, their drain-source voltage (Vds) has to be at least 400 mV peak-to-peak (mVpp). FIG. 31 gives an example of Ids-Vds characteristics of an N-channel MOS transistor. The vertical axis represents drain current (Ids), while the horizontal axis represents drain-source voltage. As can be seen from the illustrated graph, the drain current Ids of a transistor saturates at Vds=400 mV and above. The drain current does not change, however Vds increases, meaning that the transistor can work as a current source in the intended way.
The graph of FIG. 31 also indicates that Ids varies with Vds in the Vds range below 400 mV. In other words, the transistor behaves like a resistor, rather than a current source, in this voltage range.
Suppose now that the mixer circuit 100 operates at a relatively low supply voltage, e.g., Vdd=1.2 V. Under this condition, the voltage drop across resistor RL1 is at most 400 mVpp (=1200−400−400) since each transistor MN1 and MN5 requires a Vds of 400 mVpp. The other resistor RL2 behaves similarly, and the resulting differential output of the mixer circuit 100 will have a linear range of 800 mVpp (=(1200−400−400)×2).
As can be seen from the above example, Gilbert-cell mixers have a disadvantage in their narrow linear range (or low O1CP) because of the cascode structure of output transistors.
FIG. 32 illustrates a mixer circuit according to conventional technique #2. The illustrated mixer circuit 110 includes, among others, twelve MOS transistors Mn1 to Mn12, which are arranged as follows: One input terminal Vy(+) for a differential input signal Vy is connected to the gates of transistors Mn9 and Mn10, while another input terminal Vy(−) is connected to the gates of transistors Mn11 and Mn12. The drains of transistors Mn9 to Mn12 are connected to supply voltage Vcc. For another differential input signal Vx, one input terminal Vx(+) is connected to the gates of transistors Mn5 and Mn7, while another input terminal Vx(−) is connected to the gates of transistors Mn6 and Mn8. Io1 output terminal is connected to the drains of transistors Mn2 and Mn3. Io2 output terminal is connected to the drains of transistors Mn1 and Mn4.
The sources of transistors Mn1 to Mn8 are connected to the ground. The source of transistor Mn12 is connected to the gate of transistor Mn4, as well as to the drain of transistor Mn8. The source of transistor Mn11 is connected to the gate of transistor Mn3, as well as to the drain of transistor Mn7. The source of transistor Mn9 is connected to the gate of transistor Mn1, as well as to the drain of transistor Mn5. The source of transistor Mn10 is connected to the gate of transistor Mn2, as well as to the drain of transistor Mn6.
The mixer circuit 110 performs a mixing operation in the following way. Four MOS transistors Mn1 to Mn4 receive four different combinations (or sums) of differential input signals Vx and Vy at their respective gates. More specifically, transistor Mn1 receives −Vx+Vy; transistor Mn2 receives Vx+Vy; transistor Mn3 receives −Vx−Vy; and transistor Mn4 receives Vx−Vy. The drain currents of transistors Mn1 and Mn4 are added up, so are those of transistors Mn2 and Mn3. The resulting average current signals including product terms of Vx and Vy thus appear at the output terminals Io1 and Io2.
As mentioned, the outputs Io1 and Io2 of the mixer circuit 110 are current signals. Those current signals can be converted to voltage signals by placing a series resistor to each output line. Suppose now that a resistor Ra is inserted between the Io1 terminal and the node at which the drains of transistors Mn2 and Mn3 join. Likewise, suppose that a resistor Rb is inserted between the Io2 terminal and the node at which the drains of transistors Mn1 and Mn4 join.
Assuming that transistor Mn2 requires Vds of 400 mVpp for its operation at Vcc=1.2 V, the range of an output voltage developed across resistor Ra is 800 mVpp (=1200−400). Since its complementary counterpart (i.e., Mn1 and Rb) operates similarly, the linear range of differential output of the mixer circuit 110 is 1.6 Vpp (=(1.2−0.4)×2). This range is wider than that of the foregoing Gilbert-cell mixer circuit 100, under the same low supply voltage conditions (1.2 V). The mixer circuit 110 thus provides a higher O1CP.
As can be seen from the above discussion, the mixer circuit 110 of conventional technique #2 offers a wider linear range because of its single-transistor output stage. However, in the case of using a local signal (LO clock) with a rail-to-rail voltage swing, the mixer circuit 110 of conventional technique #2 does not operate properly since such a signal swing is beyond the linear range of the circuit. The following will provide more details about this problem.
The term “rail-to-rail” refers to a full swing of voltage, from the lowest to the highest of the operating range. In the case of, for example, complementary metal-oxide semiconductor (CMOS) logic, the lowest is ground (0 V), and the highest is the supply voltage.
Referring again to the mixer circuit 110 of FIG. 32, suppose that a rail-to-rail CMOS-level LO clock signal is applied to the Vx input terminals while a differential RF signal is supplied to the Vy input terminals. Assuming that the supply voltage Vcc is 1.2 V, the LO clock signal Vx takes a voltage of 1.2 V for the high state (i.e., +Vx=1.2 V) and 0 V for the low state (i.e., −Vx=0 V). Then in the case of Vy=+0.1V (i.e., +Vy=+0.1V, −Vy=−0.1V), the foregoing sums will be as follows:Vx−Vy=1.2−0.1=1.1VVx+Vy=1.2+0.1=1.3V−Vx−Vy=0−0.1=−0.1V−Vx+Vy=0+0.1=0.1VSince the operating voltage range is 0 V to 1.2 V, the mixer circuit is unable to output voltages higher than the supply voltage, or lower than the ground. The resulting clipping spoils the linearity of output signals.
Actually, the necessary condition to ensure the linearity of output signals is as follows:Vx−Vy=1.2−Vy≦1.2   (1a)Vx+Vy=1.2+Vy≦1.2   (1b)−Vx−Vy=0−Vy≧0   (1c)−Vx+Vy=0+Vy≧0   (1d)The input signal Vy must satisfy all those four conditions (1a) to (1d) under the presumption of: (a) the circuit cannot produce a voltage exceeding the supply voltage, (b) the circuit cannot produce a voltage below ground, and (c) Vx is an LO clock signal with a rail-to-rail voltage swing.
The first two conditions (1a) and (1b), or the second two conditions (1c) and (1d), result in 0≧Vy≦0, or Vy=0. This means that the mixer circuit 110 of conventional techniques #2 is unable to provide linear outputs, thus failing to operate properly with a rail-to-rail LO clock signal.
An LO clock signal with a smaller voltage swing may be used instead of the rail-to-rail signal discussed above. In general, however, reducing the voltage swing makes the mixer circuit prone to experience intrusion of unwanted phase noise or the like. To avoid such problems, the recent mixer designs tend to use a rail-to-rail LO clock. This contradicts the requirement of output linearity discussed above.
The above discussion is summarized as follows. Conventional technique #1 has a drawback in its limited linear range because of the circuit's cascode structure. A low supply voltage could lead to a narrow linearity that spoils stability of the output. It is therefore unsuitable for low voltage applications. Conventional technique #2 also has a drawback in its limited linear range when the LO clock signal swings rail-to-rail.
Mixer circuits are required to provide a sufficient linear range for accurate mixing operation, even at a low supply voltage. However, neither of the conventional techniques is suitable for such low voltage operation.